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| an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. ISO7840 , ISO7840f sllsen2b ? july 2015 ? revised april 2016 ISO7840x high-performance, 8000-v pk reinforced quad-channel digital isolator 1 1 features 1 ? signaling rate: up to 100 mbps ? wide supply range: 2.25 v to 5.5 v ? 2.25-v to 5.5-v level translation ? wide temperature range: ? 55 c to +125 c ? low-power consumption, typical 1.7 ma per channel at 1 mbps ? low propagation delay: 11 ns typical (5-v supplies) ? industry leading cmti (min): 100 kv/ s ? robust electromagnetic compatibility (emc) ? system-level esd, eft, and surge immunity ? low emissions ? isolation barrier life: > 40 years ? wide body soic-16 package and extra-wide body soic-16 package options ? safety and regulatory approvals: ? 8000-v pk reinforced isolation per din v vde v 0884-10 (vde v 0884-10):2006-12 ? 5.7-kv rms isolation for 1 minute per ul 1577 ? csa component acceptance notice 5a, iec 60950-1 and iec 60601-1 end equipment standards ? cqc certification per gb4943.1-2011 ? tuv certification per en 61010-1 and en 60950-1 ? all dw package certifications complete; dww package certifications complete per ul, vde, tuv and planned for csa and cqc 2 applications ? industrial automation ? motor control ? power supplies ? solar inverters ? medical equipment ? hybrid electric vehicles 3 description the ISO7840x device is a high-performance, quad- channel digital isolator with a 8000-v pk isolation voltage. this device has reinforced isolation certifications according to vde, csa, cqc, and tuv. the isolator provides high electromagnetic immunity and low emissions at low-power consumption, while isolating cmos or lvcmos digital i/os. each isolation channel has a logic input and output buffer separated by a silicon-dioxide (sio 2 ) insulation barrier. this device comes with enable pins that can be used to put the respective outputs in high impedance for multi-master driving applications and to reduce power consumption. the iso784 0 device has four forward and zero reverse-direction channels. if the input power or signal is lost, the default output is high for the iso784 0 device and low for the iso784 0f device. see the device functional modes section for further details. used in conjunction with isolated power supplies, this device helps prevent noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry. through innovative chip design and layout techniques, electromagnetic compatibility of the iso784 0 device has been significantly enhanced to ease system-level esd, eft, surge, and emissions compliance. the iso784 0 device is available in 16-pin soic wide-body (dw) and extra-wide body (dww) packages. device information (1) part number package body size (nom) iso784 0 iso784 0f dw (16) 10.30 mm 7.50 mm dww (16) 10.30 mm 14.0 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. simplified schematic v cci and gndi are supply and ground connections respectively for the input channels. v cco and gndo are supply and ground connections respectively for the output channels. outx gndo gndi inx v cco v cci isolation capacitor enx productfolder sample &buy technical documents tools & software support &community
2 ISO7840 , ISO7840f sllsen2b ? july 2015 ? revised april 2016 www.ti.com product folder links: ISO7840 ISO7840f submit documentation feedback copyright ? 2015 ? 2016, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 4 6 specifications ......................................................... 5 6.1 absolute maximum ratings ...................................... 5 6.2 esd ratings .............................................................. 5 6.3 recommended operating conditions ....................... 5 6.4 thermal information .................................................. 6 6.5 power dissipation characteristics ............................ 6 6.6 electrical characteristics ? 5-v supply ..................... 7 6.7 supply characteristics ? 5-v supply ......................... 7 6.8 electrical characteristics ? 3.3-v supply .................. 8 6.9 supply current characteristics ? 3.3-v supply ......... 8 6.10 electrical characteristics ? 2.5-v supply ................ 9 6.11 supply current characteristics ? 2.5-v supply ....... 9 6.12 switching characteristics ? 5-v supply ................. 10 6.13 switching characteristics ? 3.3-v supply .............. 10 6.14 switching characteristics ? 2.5-v supply .............. 11 6.15 typical characteristics .......................................... 12 7 parameter measurement information ................ 13 8 detailed description ............................................ 15 8.1 overview ................................................................. 15 8.2 functional block diagram ....................................... 15 8.3 feature description ................................................. 16 8.4 device functional modes ........................................ 20 9 application and implementation ........................ 21 9.1 application information ............................................ 21 9.2 typical application .................................................. 21 10 power supply recommendations ..................... 23 11 layout ................................................................... 24 11.1 layout guidelines ................................................. 24 11.2 layout example .................................................... 24 12 device and documentation support ................. 25 12.1 documentation support ........................................ 25 12.2 related links ........................................................ 25 12.3 community resources .......................................... 25 12.4 trademarks ........................................................... 25 12.5 electrostatic discharge caution ............................ 25 12.6 glossary ................................................................ 25 13 mechanical, packaging, and orderable information ........................................................... 25 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision a (march 2016) to revision b page ? added features 2.25 v to 5.5 v level translation ................................................................................................................ 1 ? changed the number of years for the isolation barrier life in the features section .............................................................. 1 ? vde certification is now complete ......................................................................................................................................... 1 ? changed v cco to v cci for the minimum value of the input threshold voltage hysteresis parameter in all electrical characteristics tables .............................................................................................................................................................. 7 ? added v cm to the test condition of the common-mode transient immunity parameter in all electrical characteristics tables 7 ? added the lifetime projection graphs for dw and dww packages to the safety limiting values section ......................... 17 changes from original (july 2015) to revision a page ? changed features from: industry leading cmti to: industry leading cmti (min) ............................................................. 1 ? changed the safety and regulatory approvals list of features ............................................................................................ 1 ? added features " tuv certification per en 61010-1 and en 60950-1 " ................................................................................. 1 ? changed text in the first paragraph of the description from: " certifications according to vde, csa, and cqc " . to: " certifications according to vde, csa, cqc, and tuv. " ...................................................................................................... 1 ? added the dww pinout image ............................................................................................................................................... 4 ? added the dww package to the thermal information .......................................................................................................... 6 ? changed the supply current section of electrical characteristics ? 5-v supply .................................................................... 7 ? changed the supply current section of electrical characteristics ? 5-v supply .................................................................... 8 ? changed the supply current section of electrical characteristics ? 2.5-v supply ................................................................. 9 ? changed table 2 , added the 16-dww package information .............................................................................................. 16 ? added note: " this coupler... " to the high voltage feature description section ................................................................. 16 3 ISO7840 , ISO7840f www.ti.com sllsen2b ? july 2015 ? revised april 2016 product folder links: ISO7840 ISO7840f submit documentation feedback copyright ? 2015 ? 2016, texas instruments incorporated ? added the dww package information, added " climatic category " , and deleted note 1 in table 3 .................................... 17 ? added note 1 to table 3 ..................................................................................................................................................... 17 ? changed table 4 ................................................................................................................................................................. 18 ? added the tuv and dww package information to the regulatory information section and table 5 . deleted note 1 in table 5 .............................................................................................................................................................................. 18 ? changed figure 17 .............................................................................................................................................................. 20 4 ISO7840 , ISO7840f sllsen2b ? july 2015 ? revised april 2016 www.ti.com product folder links: ISO7840 ISO7840f submit documentation feedback copyright ? 2015 ? 2016, texas instruments incorporated 5 pin configuration and functions dw and dww packages 16-pin soic top view pin functions pin i/o description name no. en2 10 i output enable 2. output pins on side 2 are enabled when en2 is high or open and in high- impedance state when en2 is low. gnd1 2 ? ground connection for v cc1 8 gnd2 9 ? ground connection for v cc2 15 ina 3 i input, channel a inb 4 i input, channel b inc 5 i input, channel c ind 6 i input, channel d nc 7 ? not connected outa 14 o output, channel a outb 13 o output, channel b outc 12 o output, channel c outd 11 o output, channel d v cc1 1 ? power supply, v cc1 v cc2 16 ? power supply, v cc2 isolation gnd1 gnd2 9 8 nc en2 10 7 ind outd 11 6 inc outc 12 5 inb outb 13 4 ina outa 14 3 gnd1 gnd2 15 2 v cc1 v cc2 16 1 5 ISO7840 , ISO7840f www.ti.com sllsen2b ? july 2015 ? revised april 2016 product folder links: ISO7840 ISO7840f submit documentation feedback copyright ? 2015 ? 2016, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values except differential i/o bus voltages are with respect to the local ground terminal (gnd1 or gnd2) and are peak voltage values. (3) maximum voltage must not exceed 6 v 6 specifications 6.1 absolute maximum ratings see (1) min max unit v cc1 , v cc2 supply voltage (2) ? 0.5 6 v voltage inx ? 0.5 v ccx + 0.5 (3) v outx ? 0.5 v ccx + 0.5 (3) en2 ? 0.5 v ccx + 0.5 (3) i o output current ? 15 15 ma surge immunity 12.8 kv t stg storage temperature ? 65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human body model (hbm), per ansi/esda/jedec js-001, all pins (1) 6000 v charged device model (cdm), per jedec specification jesd22-c101, all pins (2) 1500 (1) v cci = input-side v cc ; v cco = output-side v cc . (2) to maintain the recommended operating conditions for t j , see thermal information . 6.3 recommended operating conditions min nom max unit v cc1 , v cc2 supply voltage 2.25 5.5 v i oh high-level output current v cco (1) = 5 v ? 4 ma v cco (1) = 3.3 v ? 2 v cco (1) = 2.5 v ? 1 i ol low-level output current v cco (1) = 5 v 4 ma v cco (1) = 3.3 v 2 v cco (1) = 2.5 v 1 v ih high-level input voltage 0.7 v cci (1) v cci (1) v v il low-level input voltage 0 0.3 v cci (1) v dr signaling rate 0 100 mbps t j junction temperature (2) ? 55 150 c t a ambient temperature ? 55 25 125 c 6 ISO7840 , ISO7840f sllsen2b ? july 2015 ? revised april 2016 www.ti.com product folder links: ISO7840 ISO7840f submit documentation feedback copyright ? 2015 ? 2016, texas instruments incorporated (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report, spra953 . 6.4 thermal information iso784 0 unit thermal metric (1) dw (soic) dww (soic) 16 pins 16 pins r ja junction-to-ambient thermal resistance 78.9 78.9 c/w r jc(top) junction-to-case(top) thermal resistance 41.6 41.1 c/w r jb junction-to-board thermal resistance 43.6 49.5 c/w jt junction-to-top characterization parameter 15.5 15.2 c/w jb junction-to-board characterization parameter 43.1 48.8 c/w r jc(bottom) junction-to-case(bottom) thermal resistance n/a n/a c/w 6.5 power dissipation characteristics value unit p d maximum power dissipation by iso784 0x v cc1 = v cc2 = 5.5 v, t j = 150 c, c l = 15 pf, input a 50 mhz 50% duty cycle square wave 200 mw p d1 maximum power dissipation by side-1 of iso784 0x 40 p d2 maximum power dissipation by side-2 of iso784 0x 160 7 ISO7840 , ISO7840f www.ti.com sllsen2b ? july 2015 ? revised april 2016 product folder links: ISO7840 ISO7840f submit documentation feedback copyright ? 2015 ? 2016, texas instruments incorporated 6.6 electrical characteristics ? 5-v supply v cc1 = v cc2 = 5 v 10% (over recommended operating conditions unless otherwise noted) parameter test conditions min typ max unit v oh high-level output voltage i oh = ? 4 ma; see figure 7 v cco ? 0.4 v cco ? 0.2 v v ol low-level output voltage i ol = 4 ma; see figure 7 0.2 0.4 v v i(hys) input threshold voltage hysteresis 0.1 v cci v i ih high-level input current v ih = v cci at inx or en2 10 a i il low-level input current v il = 0 v at inx or en2 ? 10 a cmti common-mode transient immunity v i = v cci or 0 v, v cm = 1500 v; see figure 10 100 kv/ s (1) v cci = input-side v cc ; v cco = output-side v cc . 6.7 supply characteristics ? 5-v supply v cc1 = v cc2 = 5 v 10% (over recommended operating conditions unless otherwise noted) parameter test conditions supply current min typ max unit supply current disable en2 = 0 v, v i = 0 v (ISO7840f), v i = v cci (1) (ISO7840) i cc1 1.3 2 ma i cc2 0.4 0.6 en2 = 0 v, v i = v cci (ISO7840f), v i = 0 v (ISO7840) en2 = 0 v i cc1 6 8.5 ma i cc2 0.4 0.6 dc signal v i = 0 v (ISO7840f), v i = v cci (ISO7840) i cc1 1.3 2 ma i cc2 2.2 3.1 v i = v cci (ISO7840f), v i = 0 v (ISO7840) i cc1 5.9 8.6 ma i cc2 2.5 3.3 all channels switching with square wave clock input; c l = 15 pf 1 mbps i cc1 3.6 5.3 ma i cc2 2.6 3.7 10 mbps i cc1 3.8 5.4 ma i cc2 4.5 5.9 100 mbps dw package i cc1 5.1 5.9 ma i cc2 23.8 27.4 dww package i cc1 5.1 5.9 ma i cc2 23.8 28.5 8 ISO7840 , ISO7840f sllsen2b ? july 2015 ? revised april 2016 www.ti.com product folder links: ISO7840 ISO7840f submit documentation feedback copyright ? 2015 ? 2016, texas instruments incorporated 6.8 electrical characteristics ? 3.3-v supply v cc1 = v cc2 = 3.3 v 10% (over recommended operating conditions unless otherwise noted) parameter test conditions min typ max unit v oh high-level output voltage i oh = ? 2 ma; see figure 7 v cco ? 0.4 v cco ? 0.2 v v ol low-level output voltage i ol = 2 ma; see figure 7 0.2 0.4 v v i(hys) input threshold voltage hysteresis 0.1 v cci v i ih high-level input current v ih = v cci at inx or en2 10 a i il low-level input current v il = 0 v at inx or en2 ? 10 a cmti common-mode transient immunity v i = v cci or 0 v, v cm = 1500 v; see figure 10 100 kv/ s (1) v cci = input-side v cc ; v cco = output-side v cc . 6.9 supply current characteristics ? 3.3-v supply v cc1 = v cc2 = 3.3 v 10% (over recommended operating conditions unless otherwise noted) parameter test conditions supply current min typ max unit supply current disable en2 = 0 v, v i = 0 v (ISO7840f), v i = v cci (1) (ISO7840) i cc1 1.3 2 ma i cc2 0.4 0.6 en2 = 0 v, v i = v cci (1) (ISO7840f), v i = 0 v (ISO7840) i cc1 6 8.5 ma i cc2 0.4 0.6 dc signal v i = 0 v (ISO7840f), v i = v cci (1) (ISO7840) i cc1 1.3 2 ma i cc2 2.2 3 v i = v cci (1) (ISO7840f), v i = 0 v (ISO7840) i cc1 5.9 8.6 ma i cc2 2.4 3.3 all channels switching with square wave clock input; c l = 15 pf 1 mbps i cc1 3.6 5.3 ma i cc2 2.5 3.6 10 mbps i cc1 3.7 5.3 ma i cc2 3.9 5.1 100 mbps i cc1 4.5 5.8 ma i cc2 17.7 20.6 9 ISO7840 , ISO7840f www.ti.com sllsen2b ? july 2015 ? revised april 2016 product folder links: ISO7840 ISO7840f submit documentation feedback copyright ? 2015 ? 2016, texas instruments incorporated 6.10 electrical characteristics ? 2.5-v supply v cc1 = v cc2 = 2.5 v 10% (over recommended operating conditions unless otherwise noted) parameter test conditions min typ max unit v oh high-level output voltage i oh = ? 1 ma; see figure 7 v cco ? 0.4 v cco ? 0.2 v v ol low-level output voltage i ol = 1 ma; see figure 7 0.2 0.4 v v i(hys) input threshold voltage hysteresis 0.1 v cci v i ih high-level input current v ih = v cci at inx or en2 10 a i il low-level input current v il = 0 v at inx or en2 ? 10 a cmti common-mode transient immunity v i = v cci or 0 v, v cm = 1500 v; see figure 10 100 kv/ s (1) v cci = input-side v cc ; v cco = output-side v cc . 6.11 supply current characteristics ? 2.5-v supply v cc1 = v cc2 = 2.5 v 10% (over recommended operating conditions unless otherwise noted) parameter test conditions supply current min typ max unit supply current disable en2 = 0 v, v i = 0 v (devices with suffix f), v i = v cci (1) (devices without suffix f) i cc1 1.3 2 ma i cc2 0.4 0.6 en2 = 0 v, v i = v cci (1) (devices with suffix f), v i = 0 v (devices without suffix f) i cc1 6 8.5 ma i cc2 0.4 0.6 dc signal v i = 0 v (devices with suffix f), v i = v cci (1) (devices without suffix f) i cc1 1.3 2 ma i cc2 2.2 3 v i = v cci (1) (devices with suffix f), v i = 0 v (devices without suffix f) i cc1 5.9 8.6 ma i cc2 2.4 3.3 all channels switching with square wave clock input; c l = 15 pf 1 mbps i cc1 3.6 5.3 ma i cc2 2.5 3.5 10 mbps i cc1 3.7 5.3 ma i cc2 3.5 4.7 100 mbps i cc1 4.4 5.7 ma i cc2 13.9 16.4 10 ISO7840 , ISO7840f sllsen2b ? july 2015 ? revised april 2016 www.ti.com product folder links: ISO7840 ISO7840f submit documentation feedback copyright ? 2015 ? 2016, texas instruments incorporated (1) also known as pulse skew. (2) t sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. (3) t sk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. 6.12 switching characteristics ? 5-v supply v cc1 = v cc2 = 5 v 10% (over recommended operating conditions unless otherwise noted) parameter test conditions min typ max unit t plh , t phl propagation delay time see figure 7 6 11 16 ns pwd pulse width distortion (1) |t phl ? t plh | 0.55 4.1 ns t sk(o) channel-to-channel output skew time (2) same-direction channels 2.5 ns t sk(pp) part-to-part skew time (3) 4.5 ns t r output signal rise time see figure 7 1.7 3.9 ns t f output signal fall time 1.9 3.9 ns t phz disable propagation delay, high-to-high impedance output see figure 8 12 20 ns t plz disable propagation delay, low-to-high impedance output 12 20 ns t pzh enable propagation delay, high impedance-to-high output for iso784 0 10 20 ns enable propagation delay, high impedance-to-high output for iso784 0f 2 2.5 s t pzl enable propagation delay, high impedance-to-low output for iso784 0 2 2.5 s enable propagation delay, high impedance-to-low output for iso784 0f 10 20 ns t fs default output delay time from input power loss measured from the time v cc goes below 1.7 v. see figure 9 0.2 9 s t ie time interval error 2 16 ? 1 prbs data at 100 mbps 0.90 ns (1) also known as pulse skew. (2) t sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. (3) t sk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. 6.13 switching characteristics ? 3.3-v supply v cc1 = v cc2 = 3.3 v 10% (over recommended operating conditions unless otherwise noted) parameter test conditions min typ max unit t plh , t phl propagation delay time see figure 7 6 10.8 16 ns pwd pulse width distortion (1) |t phl ? t plh | 0.7 4.2 ns t sk(o) channel-to-channel output skew time (2) same-direction channels 2.2 ns t sk(pp) part-to-part skew time (3) 4.5 ns t r output signal rise time see figure 7 0.8 3 ns t f output signal fall time 0.8 3 ns t phz disable propagation delay, high-to-high impedance output see figure 8 17 32 ns t plz disable propagation delay, low-to-high impedance output 17 32 ns t pzh enable propagation delay, high impedance-to-high output for iso784 0 17 32 ns enable propagation delay, high impedance-to-high output for iso784 0f 2 2.5 s t pzl enable propagation delay, high impedance-to-low output for iso784 0 2 2.5 s enable propagation delay, high impedance-to-low output for iso784 0f 17 32 ns t fs default output delay time from input power loss measured from the time v cc goes below 1.7 v. see figure 9 0.2 9 s t ie time interval error 2 16 ? 1 prbs data at 100 mbps 0.91 ns 11 ISO7840 , ISO7840f www.ti.com sllsen2b ? july 2015 ? revised april 2016 product folder links: ISO7840 ISO7840f submit documentation feedback copyright ? 2015 ? 2016, texas instruments incorporated (1) also known as pulse skew. (2) t sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads. (3) t sk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads. 6.14 switching characteristics ? 2.5-v supply v cc1 = v cc2 = 2.5 v 10% (over recommended operating conditions unless otherwise noted) parameter test conditions min typ max unit t plh , t phl propagation delay time see figure 7 7.5 11.7 17.5 ns pwd pulse width distortion (1) |t phl ? t plh | 0.66 4.2 ns t sk(o) channel-to-channel output skew time (2) same-direction channels 2.2 ns t sk(pp) part-to-part skew time (3) 4.5 ns t r output signal rise time see figure 7 1 3.5 ns t f output signal fall time 1.2 3.5 ns t phz disable propagation delay, high-to-high impedance output see figure 8 22 45 ns t plz disable propagation delay, low-to-high impedance output 22 45 ns t pzh enable propagation delay, high impedance-to-high output for iso784 0 18 45 ns enable propagation delay, high impedance-to-high output for iso784 0f 2 2.5 s t pzl enable propagation delay, high impedance-to-low output for iso784 0 2 2.5 s enable propagation delay, high impedance-to-low output for iso784 0f 18 45 ns t fs default output delay time from input power loss measured from the time v cc goes below 1.7 v. see figure 9 0.2 9 s t ie time interval error 2 16 ? 1 prbs data at 100 mbps 0.91 ns 12 ISO7840 , ISO7840f sllsen2b ? july 2015 ? revised april 2016 www.ti.com product folder links: ISO7840 ISO7840f submit documentation feedback copyright ? 2015 ? 2016, texas instruments incorporated 6.15 typical characteristics t a = 25 c c l = 15 pf figure 1. supply current vs data rate (with 15-pf load) t a = 25 c c l = no load figure 2. supply current vs data rate (with no load) t a = 25 c figure 3. high-level output voltage vs high-level output current t a = 25 c figure 4. low-level output voltage vs low-level output current figure 5. power supply undervoltage threshold vs free-air temperature figure 6. propagation delay time vs free-air temperature low-level output current (ma) low-level output voltage (v) 0 5 10 15 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 d004d001 v cc at 2.5 v v cc at 3.3 v v cc at 5.0 v data rate (mbps) supply current (ma) 0 25 50 75 100 125 150 0 4 8 12 16 20 24 d001 i cc1 at 2.5 v i cc2 at 2.5 v i cc1 at 3.3 v i cc2 at 3.3 v i cc1 at 5 v i cc2 at 5 v data rate (mbps) supply current (ma) 0 25 50 75 100 125 150 0 2 4 6 8 10 d002 i cc1 at 2.5 v i cc2 at 2.5 v i cc1 at 3.3 v i cc2 at 3.3 v i cc1 at 5 v i cc2 at 5 v free-air temperature ( o c) power supply under-voltage threshold (v) -50 0 50 100 150 1.7 1.75 1.8 1.85 1.9 1.95 2 2.05 2.1 2.15 2.2 2.25 d005 v cc1 rising v cc1 falling v cc2 rising v cc2 falling free-air temperature ( o c) propagation delay time (ns) -60 -30 0 30 60 90 120 8 9 10 11 12 13 d006 t plh at 2.5 v t phl at 2.5 v t plh at 3.3 v t phl at 3.3 v t plh at 5.0 v t phl at 5.0 v high-level output current (ma) high-level output voltage (v) -15 -10 -5 0 0 1 2 3 4 5 6 d003 v cc at 2.5 v v cc at 3.3 v v cc at 5.0 v 13 ISO7840 , ISO7840f www.ti.com sllsen2b ? july 2015 ? revised april 2016 product folder links: ISO7840 ISO7840f submit documentation feedback copyright ? 2015 ? 2016, texas instruments incorporated 7 parameter measurement information a. the input pulse is supplied by a generator having the following characteristics: prr 50 khz, 50% duty cycle, t r 3 ns, t f 3 ns, z o = 50 . at the input, 50 resistor is required to terminate input generator signal. it is not needed in actual application. b. c l = 15 pf and includes instrumentation and fixture capacitance within 20%. figure 7. switching characteristics test circuit and voltage waveforms a. the input pulse is supplied by a generator having the following characteristics: prr 10 khz, 50% duty cycle, t r 3 ns, t f 3 ns, z o = 50 . b. c l = 15 pf and includes instrumentation and fixture capacitance within 20%. figure 8. enable/disable propagation delay time test circuit and waveform input generator (see note a) input generator (see note a) in out isolation barrier in out isolation barrier v o v o c l see note b c l see note b 50 50 0 v 3 v en en v cco r l = 1 k 1% r l = 1 k 1% v i v i v o v i t pzl v cc / 2 50% v cc v cc / 2 v oh 0 v v ol t plz 0.5 v v o v i t pzh v cc / 2 50% v cc v cc / 2 v oh 0 v 0 v t phz 0.5 v copyright ? 2016, texas instruments incorporated in out c l see note b v o v i v ol v oh v cci 0 v t r isolation barrier 50 input generator (see note a) v i v o t f t plh t phl 50% 50% 50% 50% 90% 10% copyright ? 2016, texas instruments incorporated 14 ISO7840 , ISO7840f sllsen2b ? july 2015 ? revised april 2016 www.ti.com product folder links: ISO7840 ISO7840f submit documentation feedback copyright ? 2015 ? 2016, texas instruments incorporated parameter measurement information (continued) a. c l = 15 pf and includes instrumentation and fixture capacitance within 20%. figure 9. default output delay time test circuit and voltage waveforms a. c l = 15 pf and includes instrumentation and fixture capacitance within 20%. figure 10. common-mode transient immunity test circuit in out isolation barrier en v cco c l see note a s1 gndo gndi + v cm + v oh or v ol c = 0.1 f 1% c = 0.1 f 1% v cci pass-fail criteria: the output must remain stable. copyright ? 2016, texas instruments incorporated v o out in in = 0 v (devices without suffix f) in = v (devices with suffix f) cc see note a c l v i 0 v t fs fs high v o v i 2.7 v 50% v cc v cc v ol v oh isolation barrier fs low copyright ? 2016, texas instruments incorporated 15 ISO7840 , ISO7840f www.ti.com sllsen2b ? july 2015 ? revised april 2016 product folder links: ISO7840 ISO7840f submit documentation feedback copyright ? 2015 ? 2016, texas instruments incorporated 8 detailed description 8.1 overview the iso784 0 device uses an on-off keying (ook) modulation scheme to transmit the digital data across a silicon-dioxide based isolation barrier. the transmitter sends a high-frequency carrier across the barrier to represent one digital state and sends no signal to represent the other digital state. the receiver demodulates the signal after advanced signal conditioning and produces the output through a buffer stage. if the en pin is low then the output goes to high impedance. the iso784 0 device also incorporates advanced circuit techniques to maximize the cmti performance and minimize the radiated emissions because of the high-frequency carrier and io buffer switching. the conceptual block diagram of a digital capacitive isolator, figure 11 , shows a functional block diagram of a typical channel. 8.2 functional block diagram figure 11. conceptual block diagram of a digital capacitive isolator figure 12 shows a conceptual detail of how the on-off keying scheme works. figure 12. on-off keying (ook) based modulation scheme tx in rx out carrier signal through isolation barrier tx in oscillator ook modulation transmitter emissions reduction techniques tx signal conditioning envelope detection rx signal conditioning receiver en rx out sio 2 based capacitive isolation barrier copyright ? 2016, texas instruments incorporated 16 ISO7840 , ISO7840f sllsen2b ? july 2015 ? revised april 2016 www.ti.com product folder links: ISO7840 ISO7840f submit documentation feedback copyright ? 2015 ? 2016, texas instruments incorporated (1) see regulatory information for detailed isolation ratings. 8.3 feature description table 1 lists the device features. table 1. device features part number channel direction rated isolation maximum data rate default output iso784 0 4 forward, 5700 v rms / 8000 v pk (1) 100 mbps high 0 reverse iso784 0f 4 forward, 5700 v rms / 8000 v pk (1) 100 mbps low 0 reverse (1) all pins on each side of the barrier tied together creating a two-terminal device. (2) measured from input pin to ground. 8.3.1 high voltage feature description note this coupler is suitable for 'safe electrical insulation' only within the safety ratings. compliance with the safety ratings shall be ensured by means of suitable protective circuits. table 2. package insulation and safety-related specifications over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit clr external clearance shortest terminal-to-terminal distance through air 16-dw package 8 mm 16-dww package 14.5 cpg external creepage shortest terminal-to-terminal distance across the package surface 16-dw package 8 mm 16-dww package 14.5 cti comparative tracking index din en 60112 (vde 0303-11); iec 60112; ul 746a 600 v r io isolation resistance, input to output (1) v io = 500 v, t a = 25 c 10 12 ? v io = 500 v, 100 c t a max 10 11 ? c io barrier capacitance, input to output (1) v io = 0.4 sin (2 ft), f = 1 mhz 2 pf c i input capacitance (2) v i = v cc /2 + 0.4 sin (2 ft), f = 1 mhz, v cc = 5 v 2 pf note creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. creepage and clearance on a printed-circuit board become equal in certain cases. techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. 17 ISO7840 , ISO7840f www.ti.com sllsen2b ? july 2015 ? revised april 2016 product folder links: ISO7840 ISO7840f submit documentation feedback copyright ? 2015 ? 2016, texas instruments incorporated (1) testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier. table 3. insulation characteristics parameter test conditions specification unit dw dww dti distance through the insulation minimum internal gap (internal clearance) > 21 > 21 m v iowm maximum rated working isolation voltage time dependent dielectric breakdown (tddb) test, see figure 13 and figure 14 1500 2000 v rms 2121 2828 v dc din v vde v 0884-10 (vde v 0884-10):2006-12 v iotm maximum rated transient isolation voltage v test = v iotm t = 60 sec (qualification) t= 1 sec (100% production) 8000 8000 v pk v iosm maximum surge isolation voltage for reinforced insulation test method per iec 60065, 1.2/50 s waveform, v test = 1.6 v iosm = 12800 v pk (1) (qualification) 8000 8000 v pk v iorm maximum rated repetitive peak isolation voltage 2121 2828 v pk v pr input-to-output test voltage method a, after input/output safety test subgroup 2/3, v pr = v iorm 1.2, t = 10 s, partial discharge < 5 pc 2545 3394 v pk method a, after environmental tests subgroup 1, v pr = v iorm 1.6, t = 10 s, partial discharge < 5 pc 3394 4525 method b1, v pr = v iorm 1.875, t = 1 s (100% production test) partial discharge < 5 pc 3977 5303 r s isolation resistance v io = 500 v at t s > 10 9 > 10 9 ? pollution degree 2 2 climatic category 55/125/21 55/125/21 ul 1577 v iso maximum withstanding isolation voltage v test = v iso = 5700 v rms , t = 60 sec (qualification), v test = 1.2 v iso = 6840 v rms , t = 1 sec (100% production) 5700 5700 v rms t a upto 150 c operating lifetime = 135 years stress-voltage frequency = 60 hz isolation working voltage = 1500 v rms figure 13. reinforced isolation capacitor life time projection for devices in dw package t a upto 150 c operating lifetime = 34 years stress-voltage frequency = 60 hz isolation working voltage = 2000 v rms figure 14. reinforced isolation capacitor life time projection for devices in dww package stress voltage (v rms ) time to fail (s) 500 1500 2500 3500 4500 5500 6500 7500 8500 9500 1.e+1 1.e+2 1.e+3 1.e+4 1.e+5 1.e+6 1.e+7 1.e+8 1.e+9 1.e+10 1.e+11 safety margin zone: 1800 v rms , 254 years operating zone: 1500 v rms , 135 years 20% 87.5% tddb line (<1 ppm fail rate) stress voltage (v rms ) time to fail (s) 400 1400 2400 3400 4400 5400 6400 7400 8400 9400 1.e+1 1.e+2 1.e+3 1.e+4 1.e+5 1.e+6 1.e+7 1.e+8 1.e+9 1.e+10 1.e+11 safety margin zone: 2400 v rms , 63 years operating zone: 2000 v rms , 34 years 20% 87.5% tddb line (<1 ppm fail rate) 18 ISO7840 , ISO7840f sllsen2b ? july 2015 ? revised april 2016 www.ti.com product folder links: ISO7840 ISO7840f submit documentation feedback copyright ? 2015 ? 2016, texas instruments incorporated table 4. iec 60664-1 ratings table parameter test conditions specification material group i overvoltage category / installation classification dw package rated mains voltage 600 v rms i ? iv rated mains voltage 1000 v rms i ? iii dww package rated mains voltage 1000 v rms i ? iv 8.3.1.1 regulatory information certifications for the dw package are complete. dww package certifications are complete for ul, vde and tuv and planned for csa and cqc. table 5. regulatory information vde csa ul cqc tuv certified according to din v vde v 0884-10 (vde v 0884-10):2006-12 and din en 60950-1 (vde 0805 teil 1):2011-01 approved under csa component acceptance notice 5a, iec 60950-1 and iec 60601-1 certified according to ul 1577 component recognition program certified according to gb 4943.1-2011 certified according to en 61010-1:2010 (3rd ed) and en 60950-1:2006/a11:2009/a1:2010/ a12:2011/a2:2013 reinforced insulation maximum transient isolation voltage, 8000 v pk ; maximum repetitive peak isolation voltage, 2121 v pk (dw), 2828 v pk (dww); maximum surge isolation voltage, 8000 v pk reinforced insulation per csa 60950-1-07+a1+a2 and iec 60950-1 2nd ed., 800 v rms (dw package) and 1450 v rms (dww package) max working voltage (pollution degree 2, material group i); single protection, 5700 v rms reinforced insulation, altitude 5000 m, tropical climate, 250 v rms maximum working voltage 5700 v rms reinforced insulation per en 61010-1:2010 (3rd ed) up to working voltage of 600 v rms (dw package) and 1000 v rms (dww package) 2 mopp (means of patient protection) per csa 60601- 1:14 and iec 60601-1 ed. 3.1, 250 v rms (354 v pk ) max working voltage (dw package) 5700 v rms reinforced insulation per en 60950-1:2006/a11:2009/a1:2010/ a12:2011/a2:2013 up to working voltage of 800 v rms (dw package) and 1450 v rms (dww package) certificate number: 40040142 master contract number: 220991 file number: e181974 certificate number: cqc15001121716 client id number: 77311 19 ISO7840 , ISO7840f www.ti.com sllsen2b ? july 2015 ? revised april 2016 product folder links: ISO7840 ISO7840f submit documentation feedback copyright ? 2015 ? 2016, texas instruments incorporated 8.3.1.2 safety limiting values safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. a failure of the i/o can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures. table 6. safety limiting values parameter test conditions min typ max unit i s safety input, output, or supply current r ja = 78.9 c/w, v i = 5.5 v, t j = 150 c, t a = 25 c 288 ma r ja = 78.9 c/w, v i = 3.6 v, t j = 150 c, t a = 25 c 440 r ja = 78.9 c/w, v i = 2.75 v, t j = 150 c, t a = 25 c 576 p s safety input, output, or total power r ja = 78.9 c/w, t j = 150 c, t a = 25 c 1584 mw t s maximum safety temperature 150 c the maximum safety temperature is the maximum junction temperature specified for the device. the power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. the assumed junction-to-air thermal resistance in the thermal information table is that of a device installed on a high-k test board for leaded surface mount packages. the power is the recommended maximum input voltage times the current. the junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. figure 15. thermal derating curve for safety limiting current per vde figure 16. thermal derating curve for safety limiting power per vde ambient temperature ( q c) safety limiting current (ma) 0 50 100 150 200 0 100 200 300 400 500 600 700 d014 v cc1 = v cc2 = 2.75 v v cc1 = v cc2 = 3.6 v v cc1 = v cc2 = 5.5 v ambient temperature ( q c) safety limiting power (mw) 0 50 100 150 200 0 200 400 600 800 1000 1200 1400 1600 1800 d015 power 20 ISO7840 , ISO7840f sllsen2b ? july 2015 ? revised april 2016 www.ti.com product folder links: ISO7840 ISO7840f submit documentation feedback copyright ? 2015 ? 2016, texas instruments incorporated (1) v cci = input-side v cc ; v cco = output-side v cc ; pu = powered up (v cc 2.25 v); pd = powered down (v cc 1.7 v); x = irrelevant; h = high level; l = low level ; z = high impedance (2) a strongly driven input signal can weakly power the floating v cc through an internal protection diode and cause undetermined output. (3) the outputs are in undetermined state when 1.7 v < v cci , v cco < 2.25 v. 8.4 device functional modes table 7 lists the iso784 0 functional modes. table 7. function table (1) v cci v cco input (inx) (2) output enable ( en2) output (outx) comments pu pu h h or open h normal operation: a channel output assumes the logic state of its input. l h or open l open h or open default default mode: when inx is open, the corresponding channel output goes to its default logic state. default= high for iso784 0 and low for iso784 0f. x pu x l z a low value of output enable causes the outputs to be high-impedance pd pu x h or open default default mode: when v cci is unpowered, a channel output assumes the logic state based on the selected default option. default= high for iso784 0 and low for iso784 0f. when v cci transitions from unpowered to powered-up, a channel output assumes the logic state of its input. when v cci transitions from powered-up to unpowered, channel output assumes the selected default state. x pd x x undetermined when v cco is unpowered, a channel output is undetermined (3) . when v cco transitions from unpowered to powered-up, a channel output assumes the logic state of its input 8.4.1 device i/o schematics figure 17. device i/o schematics input (device without suffix f) output enable outx v cco ~20 w inx 1.5 m w 985 w input (device with suffix f) v cci v cci v cci inx 1.5 m w 985 w v cci v cci v cci v cci enx 2 m w 1970 w v cco v cco v cco v cco copyright ? 2016, texas instruments incorporated 21 ISO7840 , ISO7840f www.ti.com sllsen2b ? july 2015 ? revised april 2016 product folder links: ISO7840 ISO7840f submit documentation feedback copyright ? 2015 ? 2016, texas instruments incorporated 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information the iso784 0 device is a high-performance, quad-channel digital isolator with a 5.7-kv rms isolation voltage. the device comes with enable pins on each side that can be used to put the respective outputs in high impedance for multi-master driving applications and reduce power consumption. the iso784 0 device uses single-ended cmos-logic switching technology. the supply voltage range is from 2.25 v to 5.5 v for both supplies, v cc1 and v cc2 . when designing with digital isolators, keep in mind that because of the single-ended design structure, digital isolators do not conform to any specific interface standard and are only intended for isolating single-ended cmos or ttl digital signal lines. the isolator is typically placed between the data controller (that is, c or uart), and a data converter or a line transceiver, regardless of the interface type or standard. 9.2 typical application figure 18. isolated data acquisition system for process control 14 13 ina outd 34 5 6 0.1 f en1 en2 7 10 inb 12 11 outc ind in c dvdd dgnd 2 gain1 24 25 26 gain0 speed pwdn ain3+ ain3 ain4+ a0 a1 ain1+ ain1 ain2+ sclk dout ref+ ref ain4 1 v cc1 16 v cc2 2, 8 9, 15 gnd1 gnd2 23 20 19 28 87 27 0.1 f p3.1 p3.0 clk somi 13 11 12 14 4 2 msp430f2132 dvss dvcc 0.1 f 14 13 outd 34 5 6 0.1 f nc en 7 10 12 11 outc ind in c 1 v cc1 16 v cc2 2, 8 9, 15 gnd1 gnd2 0.1 f ISO7840 iso7841 5 v iso 5 v iso 3.3 v 3.3 v p3.7 p3.6 18 17 3.3 v 22 avdd agnd 21 5 v iso 0.1 f ain2 13 14 17 16 15 11 12 18 ina inb outb outa outa outb 1 0.1 f 0.1 f 5 v iso 5 v iso thermo couple current shunt rtd bridge xout xin 56 p3.4 15 p3.5 16 ads1234 isolation barrier copyright ? 2016, texas instruments incorporated 22 ISO7840 , ISO7840f sllsen2b ? july 2015 ? revised april 2016 www.ti.com product folder links: ISO7840 ISO7840f submit documentation feedback copyright ? 2015 ? 2016, texas instruments incorporated typical application (continued) 9.2.1 design requirements for this design example, use the parameters shown in table 8 . table 8. design parameters parameter value supply voltage 2.25 to 5.5 v decoupling capacitor between v cc1 and gnd1 0.1 f decoupling capacitor from v cc2 and gnd2 0.1 f 9.2.2 detailed design procedure unlike optocouplers, which require external components to improve performance, provide bias, or limit current, the iso784 0 device only requires two external bypass capacitors to operate. figure 19. typical ISO7840 circuit hook-up 9.2.2.1 electromagnetic compatibility (emc) considerations many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge (esd), electrical fast transient (eft), surge, and electromagnetic emissions. these electromagnetic disturbances are regulated by international standards such as iec 61000-4-x and cispr 22. although system-level performance and reliability depends, to a large extent, on the application board design and layout, the iso784 0 device incorporates many chip-level design improvements for overall system robustness. some of these improvements include ? robust esd protection cells for input and output signal pins and inter-chip bond pads. ? low-resistance connectivity of esd cells to supply and ground pins. ? enhanced performance of high voltage isolation capacitor for better tolerance of esd, eft and surge events. ? bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance path. ? pmos and nmos devices isolated from each other by using guard rings to avoid triggering of parasitic scrs. ? reduced common mode currents across the isolation barrier by ensuring purely differential internal operation. 12 34 5 6 7 8 16 14 13 12 11 10 9 inb outc v cc2 v cc1 0.1 f 0.1 f copyright ? 2016, texas instruments incorporated ina outb ind outd inc outc v cc1 gnd1 ina inb inc ind nc gnd1 v cc2 gnd2 outa outb outc outd en2 gnd2 gnd1 gnd2 gnd1 gnd2 en ISO7840 23 ISO7840 , ISO7840f www.ti.com sllsen2b ? july 2015 ? revised april 2016 product folder links: ISO7840 ISO7840f submit documentation feedback copyright ? 2015 ? 2016, texas instruments incorporated 9.2.3 application curve the typical eye diagram of the iso784 0 device indicates low jitter and wide open eye at the maximum data rate of 100 mbps. figure 20. eye diagram at 100 mbps prbs, 5 v and 25 c 10 power supply recommendations to help ensure reliable operation at data rates and supply voltages, a 0.1- f bypass capacitor is recommended at input and output supply pins (v cc1 and v cc2 ). the capacitors should be placed as close to the supply pins as possible. if only a single primary-side power supply is available in an application, isolated power can be generated for the secondary-side with the help of a transformer driver such as texas instruments sn6501 . for such applications, detailed power supply design and transformer selection recommendations are available in the sn6501 data sheet ( sllsea0 ). 24 ISO7840 , ISO7840f sllsen2b ? july 2015 ? revised april 2016 www.ti.com product folder links: ISO7840 ISO7840f submit documentation feedback copyright ? 2015 ? 2016, texas instruments incorporated 11 layout 11.1 layout guidelines a minimum of four layers is required to accomplish a low emi pcb design (see figure 21 ). layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signal layer. ? routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits of the data link. ? placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow. ? placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100 pf/inch 2 . ? routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias. if an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to the stack to keep it symmetrical. this makes the stack mechanically stable and prevents it from warping. also the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly. for detailed layout recommendations, see the application note, digital isolator design guide ( slla284 ). 11.1.1 pcb material for digital circuit boards operating at less than 150 mbps, (or rise and fall times greater than 1 ns), and trace lengths of up to 10 inches, use standard fr-4 ul94v-0 printed circuit board. this pcb is preferred over cheaper alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and the self-extinguishing flammability-characteristics. 11.2 layout example figure 21. layout example schematic 10 mils 10 mils 40 mils fr-4 0 r ~ 4.5 keep this space free from planes, traces, pads, and vias ground plane power plane low-speed traces high-speed traces 25 ISO7840 , ISO7840f www.ti.com sllsen2b ? july 2015 ? revised april 2016 product folder links: ISO7840 ISO7840f submit documentation feedback copyright ? 2015 ? 2016, texas instruments incorporated 12 device and documentation support 12.1 documentation support 12.1.1 related documentation for related documentation, see the following: ? ads1234 24-bit analog-to-digital converter for bridge sensors , sbas350 ? digital isolator design guide , slla284 ? isolation glossary , slla353 ? msp430g2x32, msp430g2x02 mixed signal microcontroller , slas723 ? sn6501 transformer driver for isolated power supplies , sllsea0 12.2 related links the table below lists quick access links. categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. table 9. related links parts product folder sample & buy technical documents tools & software support & community ISO7840 click here click here click here click here click here ISO7840f click here click here click here click here click here 12.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.4 trademarks e2e is a trademark of texas instruments. all other trademarks are the property of their respective owners. 12.5 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 12.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 13 mechanical, packaging, and orderable information the following pages include mechanical packaging and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. 26 ISO7840 , ISO7840f sllsen2b ? july 2015 ? revised april 2016 www.ti.com product folder links: ISO7840 ISO7840f submit documentation feedback copyright ? 2015 ? 2016, texas instruments incorporated www.ti.com package outline c typ 10.639.97 2.65 max 14x 1.27 16x 0.510.31 2x 8.89 typ 0.380.25 0 - 8 0.30.1 (1.4) 0.25 gage plane 1.270.40 a note 3 10.510.1 b note 4 7.67.4 4221009/a 08/2013 soic - 2.65 mm max height dw0016b soic notes: 1. all linear dimensions are in millimeters. dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. this dimension does not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. this dimension does not include interlead flash. interlead flash shall not exceed 0.25 mm, per side. 5. reference jedec registration mo-013, variation aa. 1 16 0.25 c a b 9 8 pin 1 idarea seating plane 0.1 c see detail a typical detail a scale 1.500 27 ISO7840 , ISO7840f www.ti.com sllsen2b ? july 2015 ? revised april 2016 product folder links: ISO7840 ISO7840f submit documentation feedback copyright ? 2015 ? 2016, texas instruments incorporated www.ti.com example board layout (9.75) 0.07 max all around 0.07 min all around (9.3) 14x (1.27) 16x (1.65) 16x (0.6) 14x (1.27) 16x (2) 16x (0.6) 4221009/a 08/2013 symm soic - 2.65 mm max height dw0016b soic symm see details 1 8 9 16 symm hv / isolation option 8.1 mm clearance/creepage notes: (continued) 6. publication ipc-7351 may have alternate designs.7. solder mask tolerances between and around signal pads can vary based on board fabrication site. metal solder maskopening non solder mask defined opening solder mask details solder mask metal solder mask defined scale:4x land pattern example symm 1 8 9 16 ipc-7351 nominal 7.3 mm clearance/creepage see details 28 ISO7840 , ISO7840f sllsen2b ? july 2015 ? revised april 2016 www.ti.com product folder links: ISO7840 ISO7840f submit documentation feedback copyright ? 2015 ? 2016, texas instruments incorporated www.ti.com example stencil design 16x (1.65) 16x (0.6) 14x (1.27) (9.75) 16x (2) 16x (0.6) 14x (1.27) (9.3) 4221009/a 08/2013 soic - 2.65 mm max height dw0016b soic notes: (continued) 8. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 9. board assembly site may have different recommendations for stencil design. symm symm 1 8 9 16 hv / isolation option 8.1 mm clearance/creepage based on 0.125 mm thick stencil solder paste example scale:4x symm symm 1 8 9 16 ipc-7351 nominal 7.3 mm clearance/creepage 29 ISO7840 , ISO7840f www.ti.com sllsen2b ? july 2015 ? revised april 2016 product folder links: ISO7840 ISO7840f submit documentation feedback copyright ? 2015 ? 2016, texas instruments incorporated www.ti.com package outline c 0 -8 17.417.1 14x 1.27 16x 0.510.31 (2.286) 2.65 max 2x 8.89 0.30.1 typ 0.280.22 (1.625) a note 3 10.410.2 b note 4 14.113.9 0.25 gage plane 1.10.6 soic - 2.65 mm max height dww0016a plastic small outline 4221501/a 11/2014 notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. this dimension does not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0,15 mm per side. 4. this dimension does not include interlead flash. pin 1 id area 1 8 0.25 a b c 9 16 0.1 c seating plane see detail a typical detail a scale 1.000 30 ISO7840 , ISO7840f sllsen2b ? july 2015 ? revised april 2016 www.ti.com product folder links: ISO7840 ISO7840f submit documentation feedback copyright ? 2015 ? 2016, texas instruments incorporated www.ti.com example board layout 14x (1.27) (16.25) 0.07 max all around 0.07 min all around 16x (0.6) 16x (2) (14.25) (14.5) 16x (1.875) 16x (0.6) (16.375) 14x (1.27) soic - 2.65 mm max height dww0016a plastic small outline 4221501/a 11/2014 symm symm land pattern example standard scale:3x 1 8 9 16 notes: (continued) 5. publication ipc-7351 may have alternate designs.6. solder mask tolerances between and around signal pads can vary based on board fabrication site. metal opening solder mask non solder mask defined (preferred) solder mask details solder mask metal under solder maskopening solder mask defined pcb clearance & creepage optimized land pattern example scale:3x symm symm 1 8 9 16 31 ISO7840 , ISO7840f www.ti.com sllsen2b ? july 2015 ? revised april 2016 product folder links: ISO7840 ISO7840f submit documentation feedback copyright ? 2015 ? 2016, texas instruments incorporated www.ti.com example stencil design (16.25) 14x (1.27) 16x (2) 16x (0.6) 16x (1.875) 16x (0.6) 14x (1.27) (16.375) soic - 2.65 mm max height dww0016a plastic small outline 4221501/a 11/2014 notes: (continued) 7. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 8. board assembly site may have different recommendations for stencil design. standard solder paste example based on 0.125 mm thick stencil scale:4x symm symm 1 8 9 16 pcb clearance & creepage optimized solder paste example based on 0.125 mm thick stencil scale:4x symm symm 1 8 9 16 package option addendum www.ti.com 12-jul-2016 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples ISO7840dw active soic dw 16 40 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -55 to 125 ISO7840 ISO7840dwr active soic dw 16 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -55 to 125 ISO7840 ISO7840dww preview soic dww 16 45 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -55 to 125 ISO7840 ISO7840dwwr preview soic dww 16 1000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -55 to 125 ISO7840 ISO7840fdw active soic dw 16 40 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -55 to 125 ISO7840f ISO7840fdwr active soic dw 16 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -55 to 125 ISO7840f ISO7840fdww preview soic dww 16 45 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -55 to 125 ISO7840f ISO7840fdwwr preview soic dww 16 1000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -55 to 125 ISO7840f (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. package option addendum www.ti.com 12-jul-2016 addendum-page 2 (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant ISO7840dwr soic dw 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 q1 ISO7840fdwr soic dw 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 q1 package materials information www.ti.com 13-apr-2016 pack materials-page 1 *all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) ISO7840dwr soic dw 16 2000 367.0 367.0 38.0 ISO7840fdwr soic dw 16 2000 367.0 367.0 38.0 package materials information www.ti.com 13-apr-2016 pack materials-page 2 important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per jesd46, latest issue, and to discontinue any product or service per jesd48, latest issue. buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all semiconductor products (also referred to herein as ? components ? ) are sold subject to ti ? s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in ti ? s terms and conditions of sale of semiconductor products. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. ti assumes no liability for applications assistance or the design of buyers ? products. buyers are responsible for their products and applications using ti components. to minimize the risks associated with buyers ? products and applications, buyers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which ti components or services are used. information published by ti regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of significant portions of ti information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. ti is not responsible or liable for such altered documentation. information of third parties may be subject to additional restrictions. resale of ti components or services with statements different from or beyond the parameters stated by ti for that component or service voids all express and any implied warranties for the associated ti component or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of ti components in its applications, notwithstanding any applications-related information or support that may be provided by ti. buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. buyer will fully indemnify ti and its representatives against any damages arising out of the use of any ti components in safety-critical applications. in some cases, ti components may be promoted specifically to facilitate safety-related applications. with such components, ti ? s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. nonetheless, such components are subject to these terms. no ti components are authorized for use in fda class iii (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. only those ti components which ti has specifically designated as military grade or ? enhanced plastic ? are designed and intended for use in military/aerospace applications or environments. buyer acknowledges and agrees that any military or aerospace use of ti components which have not been so designated is solely at the buyer ' s risk, and that buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. ti has specifically designated certain components as meeting iso/ts16949 requirements, mainly for automotive use. in any case of use of non-designated products, ti will not be responsible for any failure to meet iso/ts16949. products applications audio www.ti.com/audio automotive and transportation www.ti.com/automotive amplifiers amplifier.ti.com communications and telecom www.ti.com/communications data converters dataconverter.ti.com computers and peripherals www.ti.com/computers dlp ? products www.dlp.com consumer electronics www.ti.com/consumer-apps dsp dsp.ti.com energy and lighting www.ti.com/energy clocks and timers www.ti.com/clocks industrial www.ti.com/industrial interface interface.ti.com medical www.ti.com/medical logic logic.ti.com security www.ti.com/security power mgmt power.ti.com space, avionics and defense www.ti.com/space-avionics-defense microcontrollers microcontroller.ti.com video and imaging www.ti.com/video rfid www.ti-rfid.com omap applications processors www.ti.com/omap ti e2e community e2e.ti.com wireless connectivity www.ti.com/wirelessconnectivity mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2016, texas instruments incorporated |
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